Solid State Device (SSD) architecture may face performance challenges based on how efficiently flash memory physical channels and their respective flash memory are utilized. As new SSD controller architectures emerge, SSD bandwidth may increase. However, SSD performance may still face challenges based on Input/Output (I/O) utilization of flash channels. Flash memory controllers may receive interleave or pipeline write and/or read commands for different memories or flash memory dies associated with a channel. A channel, or bus, may be connected to multiple dies, but may only permit access to one die at a time. Depending on utilization of a particular channel, I/O latency may increase.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with current technologies for managing I/O utilization of flash memory channels.